Iddq testing for high performance CMOS-the next ten years

CMOS scaling affects the subthreshold current per IC, and it directly impacts the utility of Iddq testing for CMOS devices. Continued IC manufacturing refinements enable a factor of /spl radic/2 reduction in line widths every three years. This in conjunction with an increase in chip size makes it possible to increase the number of transistors per IC by a factor between two and three. This trend in CMOS technology is expected to continue over at least the next ten years. The scaling of devices affects numerous device parameters, one being the subthreshold current commonly known as the leakage current. Assuming defect size scales with technology, it will be explained why it will become increasingly difficult to differentiate good and defective devices based upon an Iddq test methodology.

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