An NTF-enhanced time-based continuous-time sigma-delta modulator

Translation of the amplitude axis to the time axis can be a promising approach to alleviate the analog-to-digital converter’s resolution problems in low-voltage CMOS circuits. From this point of view, a noise-coupled time-based continuous-time sigma-delta modulator (TCSDM) based on the asynchronous pulse width modulator (APWM) and the time-to-digital converter (TDC) is presented. Noise-coupling is realized by extracting the time quantization error of the TDC and injecting its delayed version to the input of the APWM. By using a novel implementation of the noise-coupling technique in the proposed TCSDM, the modulator’s noise-shaping order is improved by one. Unlike the conventional noise-coupled sigma-delta modulators, in the proposed structure, the need of an extra subtractor at the quantizer input is resolved through merging the excess loop delay compensation path with the proposed noise-coupling branch. Comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed time-based modulator. To confirm the validity of the proposed structure, the effects of main circuit non-idealities in the modulator’s performance are taken into consideration and the related simulation results are investigated. A digital-friendly implementation of the quantizer in the proposed modulator makes it suitable for low-voltage nanometer CMOS technologies.

[1]  Takashi Morie,et al.  The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer , 1999 .

[2]  Mohammed Ismail,et al.  Time-based all-digital sigma–delta modulators for nanometer low voltage CMOS data converters , 2012 .

[3]  W. Martin Snelgrove,et al.  Continuous-time delta-sigma modulators for high-speed a/d conversion , 2013 .

[4]  M.Z. Straayer,et al.  A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, IEEE Journal of Solid-State Circuits.

[5]  Degang Chen,et al.  Adjustable hysteresis CMOS Schmitt triggers , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[6]  Gabor C. Temes,et al.  Noise-Coupled Delta-Sigma ADCS , 2011 .

[7]  R. T. Baird,et al.  Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging , 1995 .

[8]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[9]  E. Roza,et al.  Analog-to-digital conversion via duty-cycle modulation , 1997 .

[10]  Gordon W. Roberts,et al.  A Brief Introduction to Time-to-Digital and Digital-to-Time Converters , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Ranjit Gharpurey,et al.  Design and Analysis of a Self-Oscillating Class D Audio Amplifier Employing a Hysteretic Comparator , 2011, IEEE Journal of Solid-State Circuits.

[12]  M.Z. Straayer,et al.  A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping , 2009, IEEE Journal of Solid-State Circuits.

[13]  Gabor C. Temes,et al.  Noise-coupled continuous-time delta-sigma ADCs , 2009 .

[14]  Kenneth W. Martin,et al.  High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[15]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[16]  Weibo Li,et al.  Design of a Self-Oscillating PWM Signal Generator With a Double Integration Loop , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Arthur Gelb,et al.  Multiple-Input Describing Functions and Nonlinear System Design , 1968 .

[18]  Edgar Sánchez-Sinencio,et al.  A Continuous Time Multi-Bit $\Delta \Sigma$ ADC Using Time Domain Quantizer and Feedback Element , 2011, IEEE Journal of Solid-State Circuits.

[19]  Z. Wang,et al.  CMOS adjustable Schmitt triggers , 1991 .

[20]  Edgar Sánchez-Sinencio,et al.  A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[21]  Enrique Prefasi,et al.  Analog-to-digital conversion using noise shaping and time encoding , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Pieter Rombouts,et al.  A 5-MHz 11-Bit Self-Oscillating $\Sigma\Delta$ Modulator With a Delay-Based Phase Shifter in 0.025 mm$^2$ , 2011, IEEE Journal of Solid-State Circuits.

[23]  Ehsan Afshari,et al.  Delay-Line-Based Analog-to-Digital Converters , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[24]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[25]  Michiel Steyaert,et al.  A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[26]  Ahmed Ashry,et al.  Fast and accurate jitter simulation technique for continuous-time Σ/ spl Delta/ modulators , 2009 .

[27]  Fei Yuan.  Design techniques for time-mode noise-shaping analog-to-digital converters: a state-of-the-art review , 2014 .

[28]  Thomas Blon,et al.  A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .

[29]  Haiming Tang,et al.  Time-referenced single-path multi-bit /spl Delta//spl Sigma/ ADC using a VCO-based quantizer , 2000 .

[30]  Mohammad Yavari,et al.  A time-domain noise-coupling technique for continuous-time sigma-delta modulators , 2014 .

[31]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[32]  Maurits Ortmanns,et al.  Continuous time sigma-delta A/D conversion : fundamentals, performance limits and robust implementations , 2006 .