Performance Guarantees by Simulation of Process Networks.

[1]  Hui Zhang,et al.  Service disciplines for guaranteed performance service in packet-switching networks , 1995, Proc. IEEE.

[2]  Adam Donlin,et al.  Transaction level modeling: flows and use models , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[3]  Richard Gerber,et al.  Performance-based design of distributed real-time systems , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[4]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[5]  Erwin A. de Kock,et al.  COSY communication IP's , 2000, Proceedings 37th Design Automation Conference.

[6]  Twan Basten,et al.  Task-level timing models for guaranteed performance in multiprocessor networks-on-chip , 2003, CASES '03.

[7]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[8]  Orlando Moreira,et al.  Predictable Embedded Multiprocessor System Design , 2004, SCOPES.

[9]  Edward A. Lee,et al.  Dataflow process networks , 1995, Proc. IEEE.

[10]  Om Prakash Gangwal,et al.  A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[11]  Yongxin Zhu,et al.  Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs , 2004, CODES+ISSS.