Measuring the Impact of Memory Errors on Application  Performance

Memory reliability is a key factor in the design of warehouse-scale computers.  Prior work has focused on the performance overheads of memory fault-tolerance schemes when errors do not occur at all, and when detected but uncorrectable errors occur, which result in machine downtime and loss of availability. We focus on a common third scenario, namely, situations when hard but correctable faults exist in memory; these may  cause an “avalanche” of errors to occur on affected hardware. We expose how the hardware/software mechanisms for managing and reporting memory errors can cause severe performance degradation in systems suffering from hardware faults. We inject faults in DRAM on a real cloud server and quantify the single-machine  performance degradation for both batch and interactive workloads. We observe that for SPEC CPU2006 benchmarks, memory errors can slow down average execution time by up to 2.5<inline-formula><tex-math notation="LaTeX">$\times$</tex-math><alternatives> <inline-graphic xlink:href="gottscho-ieq1-2599513.gif"/></alternatives></inline-formula>. For an interactive web-search workload, average query latency degrades by up to 2.3<inline-formula><tex-math notation="LaTeX">$\times$</tex-math> <alternatives><inline-graphic xlink:href="gottscho-ieq2-2599513.gif"/></alternatives></inline-formula> for a light traffic load, and up to an extreme 3746<inline-formula><tex-math notation="LaTeX">$\times$</tex-math><alternatives> <inline-graphic xlink:href="gottscho-ieq3-2599513.gif"/></alternatives></inline-formula> under peak load. Our analyses of the memory error-reporting stack reveals architecture, firmware, and software opportunities to improve performance  consistency by mitigating the worst-case behavior on faulty hardware.

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