High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths
暂无分享,去创建一个
[1] S. E. Stone,et al. On-Orbit Error Rates of RHBD SRAMs: Comparison of Calculation Techniques and Space Environmental Models With Observed Performance , 2011, IEEE Transactions on Nuclear Science.
[2] Todd M. Austin,et al. DIVA: a reliable substrate for deep submicron microarchitecture design , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.
[3] Mahmut T. Kandemir,et al. An ILP formulation for reliability-oriented high-level synthesis , 2005, Sixth international symposium on quality electronic design (isqed'05).
[4] Vincenzo Piuri,et al. High-level synthesis of data paths with concurrent error detection , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).
[5] Kwang-Ting Cheng,et al. On error modeling of electrical bugs for post-silicon timing validation , 2012, 17th Asia and South Pacific Design Automation Conference.
[6] Gary Smith,et al. High-Level Synthesis: Past, Present, and Future , 2009, IEEE Design & Test of Computers.
[7] Vikram S. Adve,et al. LLVM: a compilation framework for lifelong program analysis & transformation , 2004, International Symposium on Code Generation and Optimization, 2004. CGO 2004..
[8] Jason Cong,et al. High-Level Synthesis for FPGAs: From Prototyping to Deployment , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Yun Liang,et al. High level synthesis of stereo matching: Productivity, performance, and software constraints , 2011, 2011 International Conference on Field-Programmable Technology.
[10] Olivier Sentieys,et al. VLSI implementation and complexity comparison of residue generators modulo 3 , 1998, 9th European Signal Processing Conference (EUSIPCO 1998).
[11] J. von Neumann,et al. Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .
[12] Ramesh Karri,et al. Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[13] Milo M. K. Martin,et al. SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.
[14] Ramesh Karri,et al. Computer-Aided Design of Fault-Tolerant VLSI Systems , 1996, IEEE Des. Test Comput..
[15] Eric Park Kim. Statistical Error Compensation for Robust Digital Signal Processing and Machine Learning , 2014 .
[16] David Blaauw,et al. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.
[17] William C. Mann,et al. Redundancy techniques for computing systems , 1962 .
[18] Albert Meixner,et al. Argus: Low-Cost, Comprehensive Error Detection in Simple Cores , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[19] Jason Helge Anderson,et al. LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems , 2013, TECS.