A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits

Subthreshold operation enables CMOS circuits to operate using very low supply voltages and to dissipate extremely low power with moderate performance. The dynamic threshold MOS technique (DTMOS) is an effective way to improve subthreshold circuit performance. In this paper, we propose a new body biasing technique for PMOS transistors working in the subthreshold region. In the proposed PMOS body biasing technique, the n-wells of PMOS transistors are biased with the gate output. The new technique improves circuit performance over DTPMOS and consumes less power. Simulations done using 0.18 /spl mu/m CMOS technology show that the proposed technique improves a 3-input AND gate speed by 40.1% and has a 82.3% energy-delay-product (EDP) savings over the DTPMOS scheme at 0.37 V supply voltage and 2 MHz operating frequency.