Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability

A CMOS transistor ageing analytical model is presented and the procedure that allows to extract its parameters is proposed in this paper. By using a simple, example, we show how such a model can be used to forecast the drifts of the main characteristics of a CMOS circuit Further, we demonstrate that this model can also be used to help the designer to choose and/or modify a circuit in order to minimize the hot-carrier induced degradations. Simulation results compared to the analytical study are also shown

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