Static compaction for two-pattern test sets

We propose a static compaction procedure to reduce the size of a test set comprised of two-pattern tests. The procedure reorders the tests in the test set to maximize the number of faults detected by adjacent patterns, thus allowing some of the tests to be dropped. In addition, the procedure removes redundant tests and redundant patterns, that can be omitted without reducing the fault coverage. Experimental results are presented to evaluate the effectiveness of the compaction procedure.

[1]  Dhiraj K. Pradhan,et al.  A method to derive compact test sets for path delay faults in combinational circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[2]  M. Lakshmi Narasimha Reddy.  Compact test sets for digital logic circuits , 1992 .

[3]  Soumitra Bose,et al.  Generation of compact delay tests by multiple path activation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[4]  Irith Pomeranz,et al.  Functional test generation for delay faults in combinational circuits , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[5]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[6]  Dong Sam Ha,et al.  SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits , 1991, DAC '90.

[7]  Irith Pomeranz,et al.  On compacting test sets by addition and removal of test vectors , 1994, Proceedings of IEEE VLSI Test Symposium.

[8]  Barry K. Rosen,et al.  Comparison of AC Self-Testing Procedures , 1983, ITC.

[9]  S. S. Ravi,et al.  Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..