Mapping and hierarchical self-organizing neural networks for VLSI placement

We have developed mapping and hierarchical self-organizing neural networks for placement of very large scale integrated (VLST) circuits. In this paper, we introduce MHSO and MHSO2 as two versions of mapping and hierarchical self-organizing network (MHSO) algorithms. By using the MHSO, each module in the placement wins the competition with a probability density function that is defined according to different design styles, e.g., the gate arrays and standard cell circuits. The relation between a placement carrier and movable modules is met by the algorithm's ability to map an input space (somatosensory source) into an output space where the circuit modules are located, MHSO2 is designed for macro cell circuits. In this algorithm, the shape and dimension of each module is simultaneously considered together with the wire length by a hierarchical order. In comparison with other conventional placement approaches, the MHSO algorithms have shown their distinct advantages. The results for benchmark circuits so far obtained are quite comparable to simulated annealing (SA), but the computation time is about eight-ten times faster than with SA.

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