Enhancement of Clock Delay Faults Testing
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This paper addresses the problem of simultaneous presence of multiple faults consisting of clock delay and gate transitions faults. The conditions of detecting a target multiple fault are converted into those for detecting a single stuck-at fault by adding some logic during the ATPG process. Experimental results show the effectiveness of our method by achieving nearly 100% fault efficiency.
[1] Hiroshi Takahashi,et al. Fault simulation and test generation for clock delay faults , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).