Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
暂无分享,去创建一个
[1] Kiyotaka Imai,et al. A 0.10 /spl mu/m CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).
[2] R. Holzer. A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[3] Stefan Kubicek,et al. Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime , 2000 .
[4] Dan H. Wolaver,et al. Phase-Locked Loop Circuit Design , 1991 .
[5] Zhiping Yu,et al. Impact of gate direct tunneling current on circuit performance: a simulation study , 2001 .
[6] Mohammed Ismail,et al. Adaptive Miller capacitor multiplier for compact on-chip PLL filter , 2003 .
[7] C. Hu,et al. BSIM4 gate leakage model including source-drain partition , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[8] Shen-Iuan Liu,et al. A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology , 2006, IEICE Trans. Electron..
[9] N. Nguyen,et al. A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[10] Jin-Sheng Wang,et al. A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[11] Jung-Suk Goo,et al. Direct tunneling current model for circuit simulation , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[12] T. Ono,et al. Threshold voltage fluctuation induced by direct tunnel leakage current through 1.2-2.8 nm thick gate oxides for scaled MOSFETs , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[13] P. Larsson-Edefors,et al. A gate leakage reduction strategy for future CMOS circuits , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).
[14] Xiaoyang Zeng,et al. Compact current-mode loop filter for PLL applications , 2005 .
[15] Zhongyuan Chang,et al. A self-biased PLL with current-mode filter for clock generation , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[16] Ming-Dou Ker,et al. Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.
[17] Chenming Hu,et al. Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology] , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).