Investigation of reduced models of capacitive loaded interconnects for the high-speed SI applications

The paper presents a reduced modeling method of a microstrip interconnect for the signal integrity (SI) applications. First- and second- order polynomial models of interconnects based on distributed RLCG model of a transmission line are investigated. Model accuracies are compared with exact circuit/EM co-simulations for a typical high-speed 20 µm-wide microstrip interconnect on Alumina substrate for varying interconnect lengths between 1 and 10 mm and for signal data rates between 1 and 10 Gbit/s. It is shown that the second-order model has a relative amplitude and phase errors lower than 1% from DC to 40 GHz. Also, the second-order model predicts very well the time-domain response to a pulse signal, making it suitable for the accurate prediction of the degradation of RF/digital signals in the high-speed integrated systems.

[1]  Blaise Ravelo,et al.  A New Technique of Interconnect Effects Equalization by Using Negative Group Delay Active Circuits , 2010 .

[2]  K. O. Kenneth,et al.  Affordable terahertz electronics , 2009, IEEE Microwave Magazine.

[3]  Blaise Ravelo,et al.  Experimental validation of the RC-interconnect effect equalization with negative group delay active circuit in planar hybrid technology , 2009, 2009 IEEE Workshop on Signal Propagation on Interconnects.

[4]  B. Ravelo,et al.  Application of negative group delay active circuits to reduce the 50% propagation Delay of RC-line model , 2008, 2008 12th IEEE Workshop on Signal Propagation on Interconnects.

[5]  W. Bandurski,et al.  Effect of inductance on interconnect propagation delay in VLSI circuits , 2004, Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects.

[6]  Pavan Kumar Hanumolu,et al.  EQUALIZERS FOR HIGH-SPEED SERIAL LINKS , 2005 .

[7]  W. Walker,et al.  A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS , 2005, IEEE Journal of Solid-State Circuits.

[8]  Jeremy C. Wyatt.  Signal delay in rc mesh networks , 1985 .

[9]  B. Ravelo,et al.  Equalization of interconnect propagation delay with negative group delay active circuits , 2007, 2007 IEEE Workshop on Signal Propagation on Interconnects.

[10]  Blaise Ravelo,et al.  TRANSIENT RESPONSE CHARACTERIZATION OF THE HIGH-SPEED INTERCONNECTION RLCG-MODEL FOR THE SIGNAL INTEGRITY ANALYSIS , 2011 .

[11]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[13]  Markku Rouvala,et al.  Multi-gigabit serial link emissions and mobile terminal antenna interference , 2009, 2009 IEEE Workshop on Signal Propagation on Interconnects.

[14]  W. Maichen.  When digital becomes analog - Interfaces in high speed test , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[15]  Gerard V. Kopcsay,et al.  High-Speed Signal Propagation on Lossy Transmission Lines , 1990, IBM J. Res. Dev..

[16]  J. Wells,et al.  Faster than fiber: The future of multi-G/s wireless , 2009, IEEE Microwave Magazine.