Computer Arithmetic

[1]  Hiroto Yasuura,et al.  High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.

[2]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[3]  L. Howard Pollard,et al.  Computer design and architecture , 1990 .

[4]  Janusz Rajski,et al.  Arithmetic Built-In Self-Test for Embedded Systems , 1997 .

[5]  Peter-Michael Seidel,et al.  On the design of fast IEEE floating-point adders , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[6]  Haridimos T. Vergos,et al.  Diminished-One Modulo 2n+1 Adder Design , 2002, IEEE Trans. Computers.

[7]  Eric M. Schwarz,et al.  Hardware implementations of denormalized numbers , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[8]  Chein-Wei Jen,et al.  Generalized Earliest-First Fast Addition Algorithm , 2003, IEEE Trans. Computers.

[9]  Michael J. Flynn,et al.  Systematic IEEE rounding method for high-speed floating-point multipliers , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Peter-Michael Seidel,et al.  Delay-optimized implementation of IEEE floating-point addition , 2004, IEEE Transactions on Computers.

[11]  Peter-Michael Seidel,et al.  Secondary radix recodings for higher radix multipliers , 2005, IEEE Transactions on Computers.

[12]  Eric M. Schwarz,et al.  FPU implementations with denormalized numbers , 2005, IEEE Transactions on Computers.

[13]  Tomás Lang,et al.  Double-residue modular range reduction for floating-point hardware implementations , 2006, IEEE Transactions on Computers.

[14]  Joseph R. Cavallaro,et al.  Truncated Online Arithmetic with Applications to Communication Systems , 2006, IEEE Transactions on Computers.