A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver
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[1] R. Schreier,et al. A 375-mW Quadrature Bandpass $\Delta\Sigma$ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz , 2006, IEEE Journal of Solid-State Circuits.
[2] P. Malcovati,et al. 40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW , 2008, IEEE Journal of Solid-State Circuits.
[3] Bruce A. Wooley,et al. A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator , 2008, VLSIC 2008.
[4] Yung-Yu Lin,et al. Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[5] David J. Allstot,et al. A Current Reuse Quadrature GPS Receiver in 0.13 $\mu$m CMOS , 2010, IEEE Journal of Solid-State Circuits.
[6] R. V. Veldhoven. A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.
[7] R.H.M. van Veldhoven. A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003 .
[8] B. Bakkaloglu,et al. Adaptive Blocker Rejection Continuous-Time $\Sigma \Delta $ ADC for Mobile WiMAX Applications , 2009, IEEE Journal of Solid-State Circuits.
[9] Sebastian Hoyos,et al. A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth , 2010, IEEE Journal of Solid-State Circuits.
[10] Saska Lindfors,et al. 80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers , 2003 .
[11] M. S. Kappes,et al. A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications , 2003, IEEE J. Solid State Circuits.
[12] C. Papavassiliou,et al. Quadrature ΣΔ modulators with a dynamic element matching scheme. , 2005 .
[13] B.A. Wooley,et al. A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator , 2008, IEEE Journal of Solid-State Circuits.
[14] Oliver Chiu-sing Choy,et al. A novel mismatch cancellation and I/Q channel multiplexing scheme for quadrature bandpass ΔΣ modulators , 2009, 2009 IEEE International Symposium on Circuits and Systems.
[15] Tai-Haur Kuo,et al. A wideband CMOS sigma-delta modulator with incremental data weighted averaging , 2002 .
[16] Christos Papavassiliou,et al. Quadrature /spl Sigma//spl Delta/ modulators with a dynamic element matching scheme , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.
[17] J.H. Huijsing,et al. An IF-to-Baseband $\Sigma \Delta$ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range , 2007, IEEE Journal of Solid-State Circuits.
[18] Pieter Rombouts,et al. Quadrature Mismatch Shaping for Digital-to-Analog Converters , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.
[19] Yung-Yu Lin,et al. A quadrature bandpass continuous-time delta-sigma modulator for tri-mode GSM-EDGE/UMTS/DVB-T receivers, with power scaling technique , 2010, 2010 IEEE Asian Solid-State Circuits Conference.
[20] Robert H. M. van Veldhoven,et al. A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band , 2007, IEEE Journal of Solid-State Circuits.
[21] Lucien Breems,et al. Continuous-Time Sigma-Delta Modulation for IF A/D Conversion in Radio Receivers , 2001 .
[22] F. P. Dawson,et al. A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR , 2008, IEEE J. Solid State Circuits.
[23] D. Paterson,et al. A 375mW Quadrature Bandpass /spl Delta//spl Sigma/ ADC with 90dB DR and 8.5MHz BW at 44MHz , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[24] David J. Allstot,et al. Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[25] J.H. Huijsing,et al. A quadrature data-dependent DEM algorithm to improve image rejection of a complex /spl Sigma//spl Delta/ modulator , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[26] J. Arias,et al. A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers , 2006, IEEE Journal of Solid-State Circuits.
[27] Johan H. Huijsing,et al. A quadrature data-dependent DEM algorithm to improve image rejection of a complex ΣΔ modulator , 2001 .
[28] Yung-Yu Lin,et al. A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with −97.7dBc THD and 80dB DR using low-latency DEM , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[29] Gabor C. Temes,et al. Understanding Delta-Sigma Data Converters , 2004 .
[30] T. Burger,et al. A 13.5mW, 185 MSample/s /spl Delta//spl Sigma/-modulator for UMTS/GSM dual-standard IF reception , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[31] Thomas Burger,et al. A 13.5mW, 185 MSample/s ΔΣ-modulator for UMTS/GSM dual-standard IF reception , 2001 .