Design of Low Power Content Addressable Memory

Structure of traditional content addressable memory(CAM)was analyzed,and a power model of CAM was presented.Based on the power model,a novel low-power CAM structure for ethernet MAC address recognition was designed,together with its pre-charge circuit.The circuit was simulated at 100MHz in SMIC 0.18 μm/1.8Vprocess using HSPICE.Simulation results showed that the novel CAM cell with 64 × 64array had an average lookup time of 0.8955ns,and a power consumption of 22.61μW/bit and 4.186μW/bit for writing and looking-up,respectively,which were only 12.58%and 37.9% of the conventional CAM structure.