Thermal cycling reliability of lead free solder joints on multi-terminal passive components

The ever growing demand for high performance in integrated circuit packaging is driving the requirement for use of multi-terminal passive components like interdigitated capacitors (IDCs), which inherently enable lower equivalent series inductance (ESR) as compared to its multilayer ceramic chip capacitors (MLCC) and low inductance chip capacitor (LICC) counterparts. To complement use of high functionality IDCs for maximum chip to package electrical performance, this study focuses on IDC solder joint reliability, where a combination of factors are investigated for improved package design considerations. In the current study, key surface-mount technology (SMT) parameters that impact passive component solder joint reliability were initially investigated utilizing physical failure analysis (PFA) and limited electrical testing. In addition, impact of solder composition on fatigue life was also evaluated. Though the investigation was useful in establishing qualitative trends, it had two major drawbacks: 1. Component level reliability analysis provides a step function view of the solder joint integrity, thus true characteristic life cannot be estimated as the samples are removed at specific read-points and examined. 2. Statistically significant data collection is not practical due to time/resource intensive failure analysis. To address these two shortcomings, daisy chain test vehicles were designed with ten-terminal (10T) IDCs. Specific daisy chain nets on 10T caps enabled in situ monitoring of solder joints between the IDC pad and substrate during board-level reliability (BLR) temperature cycling test by routing them to non-critical BGA locations. Detailed PFA was used to calibrate the finite element model, which was then utilized to investigate the impact of chip-cap location and orientation on IDC solder joint reliability