Verification algorithms for VLSI synthesis

A description is given of a theory for, and the application of, a general algorithm for determining whether a given multilevel Boolean function is a tautology or whether two given multilevel Boolean functions are equivalent. Four specific cases of this general algorithm are examined. These are termed the flattening method, the don't-care method, the simulation method, and the algebraic string comparison method. A single unifying algorithm frame is given for the implementation of any of these four methods, depending on parameterization. Experimental results are given which indicate that, with the exception of the don't-care method, each of these methods has a problem class in which it is clearly superior to the others. The primary application of these algorithms is as a verification tool for silicon compilation systems. However, these algorithms are also being used as the foundation for multilevel logic minimization and automatic test pattern generation programs. >

[1]  C. Y. Lee.  Representation of switching circuits by binary-decision programs , 1959 .

[2]  Gordon L. Smith,et al.  Boolean Comparison of Hardware and Flowcharts , 1982, IBM J. Res. Dev..

[3]  Louise Trevillyan,et al.  Logic Synthesis Through Local Transformations , 1981, IBM J. Res. Dev..

[4]  Louise Trevillyan,et al.  LSS: A system for production logic synthesis , 1984, IBM Journal of Research and Development.

[5]  William W. Cohen,et al.  Synthesis and Optimization of Multilevel Logic under Timing Constraints , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  J. Paul Roth,et al.  Computer Logic Testing And Verification , 1980 .

[7]  Daniel Brand.  Redundancy and Don't Cares in Logic Synthesis , 1983, IEEE Transactions on Computers.

[8]  Eugene L. Lawler,et al.  An Approach to Multilevel Boolean Minimization , 1964, JACM.

[9]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[11]  Tsutomu Sasao,et al.  HART: A hardware for logic minimization and verification , 1985 .

[12]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[13]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[14]  Hideo Fujiwara,et al.  Logic Testing and Design for Testability , 1985 .

[15]  William W. Cohen,et al.  A Rule-Based System for Optimizing Combinational Logic , 1985, IEEE Design & Test of Computers.