The design revolution of logarithmic number system architecture

Logarithmic number system (LNS) has been a trend in digital signal processing (DSP) for recent years, particularly digital image processing. LNS was been implemented in DSP processors and even as an enhancer tool in image improvements. The selection of LNS is due to the ease of operation for multiplication, division, square and square-root which been replaced by fixed-point addition, subtraction, and left- and right-shift operations, respectively. Current researches have found that LNS is possible to be a competitor and a potential replacement of floating point (FP) system in near future, as it provides comparable strength towards the latter. The other arithmetic operations, which is the addition and subtraction, however, have to face great challenges in implementations as it requires complex procedures and circuitry. As LNS potential to be a substitution of FP, there is a significant need for LNS to improve the performance. Hence, this paper outlines the evolution of the LNS architecture design and highlights the potential areas for further improvements. These enhancements will then be implemented and verified in a specific digital image processing system.

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