A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet

This paper presents a 12 bit 100MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 14-nm CMOS FinFet technology. The comparator with feedback is proposed to suppress the noise. In order to adapt to the low supply voltage application, the dynamic logic with NOR-gate is proposed. The ADC is designed in SMIC 14nm technology. It achieves SNDR of 68.96 dB and 68.36 dB at low and Nyquist input frequency, respectively, resulting in figure of merit (FoM) of 5.1 and 6.37 fJ/conversion-step, respectively.