Analytical Modeling of Parametric Yield Considering Variations in Leakage Power and Performance of Nano-Scaled Integrated Circuits

In this paper, we present an analytical method to model the joint probability density function of delay and leakage power. In order to model the joint distribution of these two parameters, they should be modeled independently through an accurate method. The manufacturing process variations as the sources of delay and leakage power variations are considered in our modeling. We also demonstrate that the proposed method is so accurate in modeling joint cumulative density function which is the very parametric yield whose predicting is the main objective of this work. Finally, the proposed method is verified by HSPICE simulations for combinational benchmark circuits in 45 nm technology. We compare the accuracy of our method with that of classic bivariate Gaussian estimation. Simulation results reveal that the mean percentage error of our proposed technique for joint cumulative density function of ISCAS85 benchmark circuits is 2.5 % by average. The average improvement achieved in accuracy of modeling joint cumulative density function through our work compared to aforementioned classic method is 17.1 % and 16.8% respectively without and with considering correlated intra-die variations. KeywordsProcess Variation; Parametric Yield; Simulation; CMOS Circuits.

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