Efficient cache design for solid-state drives

Solid-State Drives (SSDs) are data storage devices that use solid-state memory to store persistent data. Flash memory is the de facto nonvolatile technology used in most SSDs. It is well known that the writing performance of flash-based SSDs is much lower than the reading performance due to the fact that a flash page can be written only after it is erased. In this work, we present an SSD cache architecture designed to provide a balanced read/write performance for flash memory. An efficient automatic updating technique is proposed to provide a more responsive SSD architecture by writing back stable but dirty flash pages according to a predetermined set of policies during the SSD device idle time. Those automatic updating policies are also tested and compared. Simulation results demonstrate that both reading and writing performance are improved significantly by incorporating the proposed cache with automatic updating feature into SSDs.

[1]  Roberto Bez,et al.  Introduction to flash memory , 2003, Proc. IEEE.

[2]  Sang Lyul Min,et al.  A space-efficient flash translation layer for CompactFlash systems , 2002, IEEE Trans. Consumer Electron..

[3]  KimJin-Soo,et al.  A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications , 2008 .

[4]  Sang Lyul Min,et al.  Efficient Caching Algorithms for Two-level Disk Cache Hierarchies , 1997 .

[5]  Trevor N. Mudge,et al.  Integrating NAND flash devices onto servers , 2009, CACM.

[6]  Jin-Soo Kim,et al.  FAB: flash-aware buffer management policy for portable media players , 2006, IEEE Transactions on Consumer Electronics.

[7]  John F. Cigas Efficient and realistic simulation of disk cache performance , 1988, ANSS '88.

[8]  Hyojun Kim,et al.  BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage , 2008, FAST.

[9]  Rina Panigrahy,et al.  Design Tradeoffs for SSD Performance , 2008, USENIX ATC.

[10]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .

[11]  Leonidas J. Guibas,et al.  A dichromatic framework for balanced trees , 1978, 19th Annual Symposium on Foundations of Computer Science (sfcs 1978).

[12]  Dongkun Shin,et al.  Recently-evicted-first buffer replacement policy for flash storage devices , 2008, IEEE Transactions on Consumer Electronics.

[13]  Gregory R. Ganger,et al.  The DiskSim Simulation Environment Version 4.0 Reference Manual (CMU-PDL-08-101) , 1998 .

[14]  Arif Merchant,et al.  An analytic behavior model for disk drives with readahead caches and request reordering , 1998, SIGMETRICS '98/PERFORMANCE '98.

[15]  David A. Patterson,et al.  Computer Architecture, Fifth Edition: A Quantitative Approach , 2011 .

[16]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[17]  Alan Jay Smith,et al.  Disk cache—miss ratio analysis and design considerations , 1983, TOCS.

[18]  Jeffrey Katcher,et al.  PostMark: A New File System Benchmark , 1997 .

[19]  Sooyong Kang,et al.  Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices , 2009, IEEE Transactions on Computers.