Design methodology for GMICRO/500 TRON microprocessor

Describes the design methodology used for the architecture of the GMICRO/500 TRON CISC superscalar microprocessor. Its minimum performance goal is 50 MHz, 100 VAX-MIPS at 5 V. This severe goal and the CISC superscalar architecture make the design time long and require a lot of manpower and computer resources. The C language and Unix environment are used to reduce the cost of the logic simulation. Synopsis and GDT are used to accelerate the logic design and the cell/macro design. A supercomputer is used to shorten the gate-level simulation time. The total design manpower is under 603 man-months.<<ETX>>

[1]  David R. Ditzel,et al.  Introduction to the CRISP Instruction Set Architecture , 1987, COMPCON.

[2]  F. Arakawa,et al.  A CMOS 50 MHz CISC superscalar microprocessor , 1993, Symposium 1993 on VLSI Circuits.

[3]  Susumu Narita,et al.  GMICRO/500 microprocessor: pipeline structure of superscalar architecture , 1992, Proceedings [1992] The Ninth TRON Project Symposium.

[4]  Raymond Peck,et al.  Design methodology for a MIPS compatible embedded control processor , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.