Design and fabrication of depletion GaAs LSI high-speed 32-bit adder

A GaAs LSI 32-bit adder implemented in BFL (buffered FET logic) gates has been designed and fabricated to demonstrate the feasibility of high-performance depletion GaAs LSI. Power dissipation reduction has been successfully achieved by reducing the number of level-shifting diodes to one, conforming with the FET threshold voltage (-0.5 V) and supply voltages (2 V, -1 V). Computer simulation was carried out with the interconnect parasitic capacitance included. In the IC, carry-look-ahead operation was utilized for realizing high-speed performance for 32-bit addition. The fabricated IC implementation required 420 gates, including 2100 FETs and 420 diodes, within a chip area of 4.6 mm/spl times/2.5 mm. High-speed performance was evaluated by packaging an IC chip. A maximum addition time of 2.9 ns with power dissipation of 1.2 W was obtained.

[1]  H. Ishikawa,et al.  A GaAs 1K static RAM using tungsten-silicide gate self alignment technology , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  S. Asai,et al.  Depletion-type GaAs MSI 32b adder , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  R. Van Tuyl,et al.  High-speed GaAs MSI , 1976, 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  A. F. Podell,et al.  A GaAs MSI word generator operating at 5 Gbits/s data rate , 1982 .

[5]  P. Asbeck,et al.  A high-speed LSI GaAs 8x8 bit parallel multiplier , 1982, IEEE Journal of Solid-State Circuits.

[6]  R. Tuyl,et al.  High-speed integrated logic with GaAs MESFET's , 1974 .