Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

Excess source and drain (S/D) recess depth (<inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula>) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (<inline-formula> <tex-math notation="LaTeX">$I_{off}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula>) in three-stacked NS channels and parasitic bottom transistor (<inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula>), gate capacitance (<inline-formula> <tex-math notation="LaTeX">$C_{gg}$ </tex-math></inline-formula>), intrinsic switching delay time (<inline-formula> <tex-math notation="LaTeX">$\tau _{d}$ </tex-math></inline-formula>), and static power dissipation (<inline-formula> <tex-math notation="LaTeX">$P_{static}$ </tex-math></inline-formula>) are investigated quantitatively according to the <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula> variations. More S/D dopants diffuse into the <inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula> with the deeper <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula>, so the <inline-formula> <tex-math notation="LaTeX">$I_{off}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> increase due to raised current flowing through the <inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula>. Especially, the <inline-formula> <tex-math notation="LaTeX">$I_{off}$ </tex-math></inline-formula> of PFETs remarkably increases above the certain <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">$T_{SD,critical}$ </tex-math></inline-formula>) compared to NFETs. Furthermore, the <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> contribution of each channels having the <inline-formula> <tex-math notation="LaTeX">$T_{SD,critical}$ </tex-math></inline-formula> is the largest at the top NS channel and the <inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula> has the ignorable <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The <inline-formula> <tex-math notation="LaTeX">$C_{gg}$ </tex-math></inline-formula> also increases with the deeper <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula> by increasing parasitic capacitance, but fortunately, the <inline-formula> <tex-math notation="LaTeX">$\tau _{d}$ </tex-math></inline-formula> decreases simultaneously due to the larger increasing rate of the <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> than that of the <inline-formula> <tex-math notation="LaTeX">$C_{gg}$ </tex-math></inline-formula> for all SoC applications. However, the <inline-formula> <tex-math notation="LaTeX">$P_{static}$ </tex-math></inline-formula> enormously increases with the deeper <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula>, and low power application is the most sensitive to the <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula> variations among the SoC applications. Comprehensive analysis of the inevitable <inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula> effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.

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