Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

Abstract We report an experimental study of the carrier transport in [1 1 0]-oriented long channel tri-gate (TG) and omega-gate (ΩG) silicon nanowire (SiNW) transistors cross-section down to 11 nm × 10 nm. Electron and hole mobilities have been measured down to 20 K to evaluate the contribution from the dominant scattering mechanisms. We have studied and discussed the influence of channel shape, channel width and strain effect on carrier mobility. In particular, we have shown that the transport properties are mainly driven by the relative contribution of the different inversion surfaces, without noticeable differences between TG and ΩGNWs. We have also demonstrated the effectiveness of an additional uniaxial tensile strain in NMOS NWs down to 10 nm width.

[1]  A. Toriumi,et al.  In-plane mobility anisotropy and universality under uni-axial strains in nand p-MOS inversion layers on (100), [110], and (111) Si , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[2]  Lidija Sekaric,et al.  Measurement of carrier mobility in silicon nanowires. , 2008, Nano letters.

[3]  G. Ghibaudo,et al.  Low temperature characterization of effective mobility in uniaxially and biaxially strained N-MOSFETs , 2005 .

[4]  K. Saraswat,et al.  Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[5]  Scott E. Thompson,et al.  Hole mobility in silicon inversion layers: Stress and surface orientation , 2007 .

[6]  T. Hiramoto,et al.  Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI , 2008, 2008 Symposium on VLSI Technology.

[7]  G. Ghibaudo,et al.  Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width , 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

[8]  T. Ohmi,et al.  Very High Carrier Mobility for High-Performance CMOS on a Si(110) Surface , 2007, IEEE Transactions on Electron Devices.

[9]  G. Reimbold,et al.  Study of piezoresistive properties of advanced CMOS transistors: Thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate Nanowires , 2012, 2012 International Electron Devices Meeting.

[10]  O. Faynot,et al.  Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width , 2013, IEEE Transactions on Electron Devices.

[11]  S. Takagi,et al.  On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation , 1994 .

[12]  N. Sugiyama,et al.  [110]-surface strained-SOI CMOS devices , 2005, IEEE Transactions on Electron Devices.

[13]  S. Takagi,et al.  On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration , 1994 .

[14]  J. Welser,et al.  Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors , 1996 .

[15]  P. Solomon,et al.  Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness , 2003 .

[16]  Stephane Monfray,et al.  Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width , 2013 .

[17]  T. Numata,et al.  Short-channel performance and mobility analysis of <110>- and <100>-oriented tri-gate nanowire MOSFETs with raised source/drain extensions , 2010, 2010 Symposium on VLSI Technology.

[18]  C. Carabasse,et al.  Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors , 2010, 2010 International Electron Devices Meeting.

[19]  M. Rudan,et al.  Effects of the Band-Structure Modification in Silicon Nanowires with Small Diameters , 2006, 2006 European Solid-State Device Research Conference.

[20]  M. Saitoh,et al.  Carrier Transport in (110) nMOSFETs: Subband Structures, Non-Parabolicity, Mobility Characteristics, and Uniaxial Stress Engineering , 2006, 2006 International Electron Devices Meeting.

[21]  C.-Y. Yu,et al.  Mobility-enhancement technologies , 2005, IEEE Circuits and Devices Magazine.

[22]  G. Reimbold,et al.  Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[23]  Isabelle Ferain,et al.  Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors , 2011, Nature.

[24]  Scott E. Thompson,et al.  Strain effects on three-dimensional, two-dimensional, and one-dimensional silicon logic devices: Predicting the future of strained silicon , 2010 .

[25]  S. Thompson,et al.  Strain Effect in Semiconductors , 2010 .

[26]  E. Gusev,et al.  The role of Si orientation and temperature on the carrier mobility in metal oxide semiconductor field-effect transistors with ultrathin HfO2 gate dielectrics , 2006 .