A HIERERACHICAL, E RROR-TOLERANT C OMPACTOR

This paper describes a compactor that is practical for compacting whole chips that are designed hierarchically, and can produce a reasonable result in spite of the layout being over-constrained. The layout produced is good enough to be used in high volume chips. The compactor is currently used in a cell layout system and a chip assembly tool. Introduetlon Many different compactors have been written; this paper describes the features particular to the compactor in VTrs tools. It is a one dimensional compactor, unlike the compactors reported in 1,6J. A one dimensional compactor makes smaller changes to the input layout, so designers can predict what will happen when they actually use the compactor. The most important features are: • The critical path, the objects that determine the overall size, of the layout can be displayed, telling designers just what they can do to improve the layout.