A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2/High- $k$ Stacked Gate-Oxide Structure

A compact 2-D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of double-gate tunnel FET (DG TFETs) with a SiO2/High-k stacked gate-oxide structure is proposed in this paper. Poisson's equation has been solved using parabolic approximation method to model the channel potential. The band-to-band tunneling generation rate has been expressed as a function of channel electric field derived from the channel potential and then integrated analytically over the channel thickness to derive the drain current of the stacked-gate DG TFETs using the shortest tunneling path (Ltmin) concept. The effect of source/drain depletion regions has been included for the better accuracy of the proposed model. The maximum transconductance method has finally been used to extract the threshold voltage from the drain current of the device. The effects of various device parameters on the channel potential, drain current, and threshold voltage have been investigated. The model results have been compared with the simulation data obtained using the commercially available ATLAS 2-D device simulator from SILVACO for the validity of the proposed model.

[1]  K. Boucart,et al.  Double-Gate Tunnel FET With High-κ Gate Dielectric , 2008 .

[2]  Subir Kumar Sarkar,et al.  Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor , 2016 .

[3]  G. P. Mishra,et al.  A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET) , 2015 .

[4]  Chenming Hu,et al.  Green transistor as a solution to the IC power crisis , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[5]  Chi On Chui,et al.  Electrostatic Modeling and Insights Regarding Multigate Lateral Tunneling Transistors , 2013, IEEE Transactions on Electron Devices.

[6]  Chi On Chui,et al.  A Quasi-Analytical Model for Double-Gate Tunneling Field-Effect Transistors , 2012, IEEE Electron Device Letters.

[7]  C. van Hoof,et al.  Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions , 2010, IEEE Transactions on Electron Devices.

[8]  M. J. Kumar,et al.  An Accurate Compact Analytical Model for the Drain Current of a TFET From Subthreshold to Strong Inversion , 2015, IEEE Transactions on Electron Devices.

[9]  M. White,et al.  The effect of channel implants on MOS transistor characterization , 1987, IEEE Transactions on Electron Devices.

[10]  T. Chiang,et al.  A new analytical threshold voltage model for symmetrical double-gate MOSFETs with high- k gate dielectrics , 2007 .

[11]  Doris Schmitt-Landsiedel,et al.  Complementary tunneling transistor for low power application , 2004 .

[12]  M. J. Kumar,et al.  Doping-Less Tunnel Field Effect Transistor: Design and Investigation , 2013, IEEE Transactions on Electron Devices.

[13]  S. Jit,et al.  Effects of Electrostatically Doped Source/Drain and Ferroelectric Gate Oxide on Subthreshold Swing and Impact Ionization Rate of Strained-Si-on-Insulator Tunnel Field-Effect Transistors , 2015, IEEE Transactions on Nanotechnology.

[14]  K. Boucart,et al.  Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric , 2007, IEEE Transactions on Electron Devices.

[15]  S. Jit,et al.  A Novel Four-Terminal Ferroelectric Tunnel FET for Quasi-Ideal Switch , 2015, IEEE Transactions on Nanotechnology.

[16]  K. Maex,et al.  Tunnel field-effect transistor without gate-drain overlap , 2007 .

[17]  Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor , 2013 .

[18]  E. Kane.  Zener tunneling in semiconductors , 1960 .

[19]  G. P. Mishra,et al.  A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance , 2015 .

[20]  Jin He,et al.  A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors , 2012, 2012 International Electron Devices Meeting.

[21]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.

[22]  B. Raj,et al.  Compact channel potential analytical modeling of DG-TFET based on Evanescent-mode approach , 2015 .

[23]  Seyed Ebrahim Hosseini,et al.  An analytical model for transfer characteristics and sub-threshold swings in double-gate tunnel FETs , 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

[24]  J.C.S. Woo,et al.  The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor , 2008, IEEE Transactions on Electron Devices.

[25]  B. Sorée,et al.  Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor , 2010 .

[26]  M. Jagadesh Kumar,et al.  Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport , 2014, IEEE Transactions on Electron Devices.

[27]  I. Eisele,et al.  Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering , 2005, IEEE Transactions on Electron Devices.

[28]  K. K. Young.  Short-channel effect in fully depleted SOI MOSFETs , 1989 .

[29]  J. Kuo,et al.  Modeling the fringing electric field effect on the threshold voltage of FD SOI nMOS devices with the LDD/sidewall oxide spacer structure , 2003 .

[30]  M. J. Kumar,et al.  Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor , 2011, IEEE Transactions on Electron Devices.