Design of a Fault-Tolerant DRAM with New On-Chip ECC

Soft errors induced by incident alpha particles are one of the most serious problems at present and in future VLSI dynamic random-access memory (DRAM) development. Alpha particles emitted during radioactive decay of uranium and thorium, contained in minute proportions in packaging materials [1], have been shown to cause 98% failures that occur during normal operation of the DRAM chip [2,3]. On-line hard and medium errors are relatively very low in a well-designed chip. Hard errors are caused by permanent defects such as stuck-at faults, while the causes of medium errors are obscure, and frequently these errors result due to patternsensitive leakage currents. Such errors are virtually eliminated by testing the chips rigorously after manufacture. A small fraction of failures are due to transients like the voltage spikes and man-made statics. By introducing suitable filtering circuits these sources of transient errors can be sufficiently suppressed. But the alpha-particle-induced soft errors are becoming more and more critical as the the cell dimension is reducing.