Input space adaptive design: a high-level methodology for energy and performance optimization
暂无分享,去创建一个
Niraj K. Jha | Ganesh Lakshminarayana | Anand Raghunathan | Weidong Wang | N. Jha | A. Raghunathan | G. Lakshminarayana | Weidong Wang
[1] Miodrag Potkonjak,et al. Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] P. Fernandez,et al. An input dependent algorithm for the inverse discrete wavelet transform , 1998, Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284).
[3] Farid N. Najm,et al. Towards a high-level power estimation capability , 1995, ISLPED '95.
[4] Antonio Ortega,et al. DCT computation with minimal average number of operations , 1997, Electronic Imaging.
[5] Andrew A. Chien,et al. Architectural adaptation in MORPH , 1998, Other Conferences.
[6] J. Rabaey,et al. Behavioral Level Power Estimation and Exploration , 1997 .
[7] Wayne P. Burleson,et al. Reconfiguration for power saving in real-time motion estimation , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).
[8] Sujit Dey,et al. Common-case computation: a high-level technique for power and performance optimization , 1999, DAC '99.
[9] Niraj K. Jha,et al. FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .
[11] Marios C. Papaefthymiou,et al. Precomputation-based sequential logic optimization for low power , 1994, ICCAD '94.
[12] Srivaths Ravi,et al. Integrating variable-latency components into high-level synthesis , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[13] Niraj K. Jha,et al. High-level synthesis of low-power control-flow intensive circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] Marios C. Papaefthymiou,et al. Precomputation-based sequential logic optimization for low power , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[15] Reconfigurable low energy multiplier for multimedia system design , 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.
[16] Giovanni De Micheli,et al. Synthesis and Optimization of Digital Circuits , 1994 .
[17] R. Wells. Applied Coding and Information Theory for Engineers , 1998 .
[18] Srinivas Devadas,et al. Application-specific memory management for embedded systems using software-controlled caches , 2000, Proceedings 37th Design Automation Conference.
[19] Niraj K. Jha,et al. FACT: a framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[20] Alfred V. Aho,et al. Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.
[21] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[22] Luca Benini,et al. Telescopic units: a new paradigm for performance optimization of VLSI designs , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] Radu Marculescu,et al. Information theoretic measures of energy consumption at register transfer level , 1995, ISLPED '95.