Memory controller and electronic device having the memory controller

Provided is a memory controller capable of receiving a plurality of addresses of a nonvolatile memory device and controlling a plurality of planes of the nonvolatile memory device to perform an operating command at the same time. The memory controller comprises: a first interface configured to receive, from a host, a first command, a first address corresponding to the first command, a second address, an address state separation command separating the first and second addresses, and a second command corresponding to the second address; and a microprocessor configured to control to decode the first command, map the first address, and perform the decoded first command in a nonvolatile memory device using the first address in which the decoded first command is mapped, and to determine the correlation between the first and second addresses with reference to the address state separation command, wherein the correlation determines whether the first and second commands are respectively performed in the first and second addresses at the same time.