Design methodology for system LSI with TIS (trench‐isolated transistor using sidewall gate)

The author proposes a design methodology that uses TIS for a system LSI chip that consists primarily of NAND and NOR gate logic. They use a system LSI chip for communication as an example to show that the planar + TIS architecture is effective in reducing the pattern area in a system LSI chip that is designed by using a cell library. The planar + TIS architecture uses the TIS architecture for parts in which the transistor channel width is large and the planar architecture for parts in which it is small. When the minimum channel width of a transistor is set to 5F (F is the minimum line width), the pattern area consisting of the element area and element isolation area can be reduced to 25% to 36% of the area for the planar architecture by setting the trench depth to D = 2F or 4.5F. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(11): 1–12, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20259