Distributed power network co-design with on-chip power supplies and decoupling capacitors

With each technology generation, the power delivery network becomes larger and more complicated, making the system analysis process computationally complex. The rising number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. Interactions among the on-chip power supplies, decoupling capacitors, and load circuitry are investigated in this paper. The on-chip power supplies and decoupling capacitors within the power network are simultaneously co-designed and placed. The effect of physical distance on the power supply noise is investigated. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.

[1]  Sanjay Pant,et al.  Power Grid Physics and Implications for CAD , 2007, IEEE Design & Test of Computers.

[2]  Malgorzata Marek-Sadowska,et al.  A study of decoupling capacitor effectiveness in power and ground grid networks , 2009, 2009 10th International Symposium on Quality Electronic Design.

[3]  G. Venezian,et al.  On the resistance between two points on a grid , 1994 .

[4]  Meeta Sharma Gupta,et al.  System level analysis of fast, per-core DVFS using on-chip switching regulators , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[5]  Eby G. Friedman,et al.  Multi-Voltage CMOS Circuit Design: Kursun/Multi-Voltage CMOS Circuit Design , 2006 .

[6]  Patrik Larsson,et al.  di/dt Noise in CMOS Integrated Circuits , 1997 .

[7]  Eby G. Friedman,et al.  Multi-voltage CMOS Circuit Design , 2006 .

[8]  R Edelson.  CMOS integrated circuits. , 1989, Biomedical instrumentation & technology.

[9]  Eby G. Friedman,et al.  Power Distribution Networks with On-Chip Decoupling Capacitors , 2007 .

[10]  Eby G. Friedman,et al.  On-chip point-of-load voltage regulator for distributed power supplies , 2010, GLSVLSI '10.

[11]  Huajie Chen,et al.  On-chip decoupling capacitor optimization for high-performance VLSI design , 1995, 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.

[12]  Avinoam Kolodny,et al.  Effective Radii of On-Chip Decoupling Capacitors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Emre Salman,et al.  Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  T. Karnik,et al.  Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.

[15]  Eby G. Friedman,et al.  Fast algorithms for IR voltage drop analysis exploiting locality , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[16]  Larry D. Smith,et al.  Power distribution system design methodology and capacitor selection for modern CMOS technology , 1999 .

[17]  Eby G. Friedman,et al.  An area efficient fully monolithic hybrid voltage regulator , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[18]  Massoud Pedram,et al.  Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.