DFT advances in Motorola's Next-Generation 74xx PowerPC/sup TM/ microprocessor
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Dawit Belete | Robert F. Molyneaux | Robert Bailey | Rajesh Raina | Javier Prado | Ashutosh Razdan | Vikram Khosa | R. Raina | Ashu Razdan | D. Belete | R. Molyneaux | R. Bailey | Vikram Khosa | J. Prado
[1] Craig Hunter,et al. Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessor , 1994, Proceedings., International Test Conference.
[2] Craig Hunter,et al. Integrated diagnostics for embedded memory built-in self test on PowerPC/sup TM/ devices , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.
[3] Carol Pyron,et al. Next generation PowerPC/sup TM/ microprocessor test strategy improvements , 1997, Proceedings International Test Conference 1997.
[4] Bruce Long,et al. DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[5] Jacob Savir,et al. Built In Test for VLSI: Pseudorandom Techniques , 1987 .
[6] M. Abadir,et al. Design-for-test methodology for Motorola PowerPC/sup TM/ microprocessors , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[7] Anjali Kinra. Towards reducing "functional only" fails for the UltraSPARC/sup TM/ microprocessors , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[8] Timothy J. Wood. The test and debug features of the AMD-K7/sup TM/ microprocessor , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[9] Nandu Tendolkar,et al. At-speed testing of delay faults for Motorola's MPC7400, a PowerPC/sup TM/ microprocessor , 2000, Proceedings 18th IEEE VLSI Test Symposium.
[10] Craig Hunter,et al. The PowerPC 603 microprocessor: an array built-in self test mechanism , 1994, Proceedings., International Test Conference.
[11] Peter Wohl,et al. Test generation for ultra-large circuits using ATPG constraints and test-pattern templates , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[12] D. Reid,et al. 450 MHz PowerPC/sup TM/ microprocessor with enhanced instruction set and copper interconnect , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[13] R. Raina,et al. Efficient Testing Of Clock Regenerator Circuits In Scan Designs , 1997, Proceedings of the 34th Design Automation Conference.
[14] C. Pyron,et al. DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. , 1999 .
[15] D.R. Bearden,et al. A 780 MHz PowerPC/sup TM/ microprocessor with integrated L2 cache , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).