A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator
暂无分享,去创建一个
[1] Frank O'Mahony,et al. A 10-GHz global clock distribution using coupled standing-wave oscillators , 2003 .
[2] D. Leeson. A simple model of feedback oscillator noise spectrum , 1966 .
[3] M.J. Kobrinsky,et al. Comparisons of conventional, 3-D, optical, and RF interconnects for on-chip clock distribution , 2004, IEEE Transactions on Electron Devices.
[4] A. Iwata,et al. 17GHz Fine Grid Clock Distribution with Uniform-Amplitude Standing-Wave Oscillator , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..
[5] Li Lin,et al. A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[6] Joungho Kim,et al. A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network , 2006, IEEE Microwave and Wireless Components Letters.
[7] K.L. Shepard,et al. Uniform-phase uniform-amplitude resonant-load global clock distributions , 2005, IEEE Journal of Solid-State Circuits.