A real-time VLSI median filter employing two-dimensional bit-propagating architecture
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[1] Roberto Roncella,et al. 70-MHz 2- mu m CMOS bit-level systolic array median filter , 1993 .
[2] Chung Len Lee,et al. Bit-sliced median filter design based on majority gate , 1992 .
[3] Levent Onural,et al. Design and implementation of a general-purpose median filter unit in CMOS VLSI , 1990 .
[4] Chin-Hsing Chen,et al. Data dependence analysis and bit-level systolic arrays of the median filter , 1998, IEEE Trans. Circuits Syst. Video Technol..
[5] T. Shibata,et al. A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[6] Gregory T. A. Kovacs,et al. A high-speed median circuit , 1997 .