Multilayer Power Delivery Network Design for Reduction of EMI and SSN in High-Speed Microprocessor System

In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stack up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.