Architecture and design of a second-level cache chip with copy-back and 160 MB/s burst-transfer features

The authors describe the architecture and design of a second-level cache chip which supports high-speed (160-Mb/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. This chip includes a 32-kB data memory as well as a 42-kb tag memory and 21.7 K-gate logic, and it supports a 50-MHz CPU. Performance and design results are presented

[1]  K. Sato,et al.  A circuit design of 32Kbyte integrated cache memory , 1988, Symposium 1988 on VLSI Circuits.

[2]  T. Watanabe.  An 8Kbyte intelligent cache memory , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.