Discussion group: Extrinsic breakdown characteristics: How to avoid them — How to detect them ?

Integrated circuits are complex with up to billions of devices. Intrinsic device characteristics are easy to monitor with reasonable sample sizes. However extrinsic fails are not that easy to monitor. Required failure rates are approaching zero with a “ZERO DEFECT” strategy. But also the verification of single digit ppm failure rates require enormous measurement resources to detect some extrinsics and in a second step to avoid them. At the end of the day the extrinsic fails “hurt” the semiconductor manufacturer. Therefore the investigation into extrinsics is absolutely necessary and the discussion point of this group. How can the extrinsics being detected for all the different process reliability topics, such as breakdown of gate oxides or other dielectrics, negative bias temperature instability, electromigration, hot carrier degradation, plasma induced damage, via integrity etc. In a second step the task is to avoid these extrinsics. How can we achieve this? Can continuous process improvement, product screening/burn in, intelligent circuitry with redundancy or self-repair help?