Fast thermal analysis for fixed-outline 3D floorplanning
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[1] Evangeline F. Y. Young,et al. Planning Massive Interconnects in 3-D Chips , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Takeshi Yoshimura,et al. Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] Tsung-Yi Ho,et al. Bus-driven floorplanning with thermal consideration , 2013, Integr..
[4] Di Long,et al. Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation , 2006, 2007 Asia and South Pacific Design Automation Conference.
[5] Jason Cong,et al. A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.
[6] Wei Zhong,et al. Whitespace insertion for through-silicon via planning on 3-D SoCs , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[7] W. Press,et al. Numerical Recipes: The Art of Scientific Computing , 1987 .
[8] Igor L. Markov,et al. Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[9] Xiaodong Liu,et al. An integrated algorithm for 3D-IC TSV assignment , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[10] Evangeline F. Y. Young,et al. Fixed-outline thermal-aware 3D floorplanning , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[11] Sung Kyu Lim,et al. Multi-layer floorplanning for reliable system-on-package , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[12] Chip-Hong Chang,et al. Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).
[13] Andy Heinig,et al. Thermal analysis and optimization of 2.5D and 3D integrated systems with Wide I/O memory , 2014, Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).
[14] Charlie Chung-Ping Chen,et al. 3D thermal-ADI: an efficient chip-level transient thermal simulator , 2003, ISPD '03.
[15] Jie Meng,et al. Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints , 2012, DAC Design Automation Conference 2012.
[16] Takeshi Yoshimura,et al. Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints , 2010, Integr..
[17] Hai Zhou,et al. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits , 2007, ICCAD 2007.
[18] Jason Cong,et al. LP based white space redistribution for thermal via planning and performance optimization in 3D ICs , 2008, 2008 Asia and South Pacific Design Automation Conference.
[19] Yoji Kajitani,et al. VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Kurt Mehlhorn,et al. LEDA: a platform for combinatorial and geometric computing , 1997, CACM.
[21] Xin Li,et al. A novel thermal optimization flow using incremental floorplanning for 3D ICs , 2009, 2009 Asia and South Pacific Design Automation Conference.
[22] Yuan Xie,et al. Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[23] Kaustav Banerjee,et al. Multiple Si layer ICs: motivation, performance analysis, and design implications , 2000, Proceedings 37th Design Automation Conference.
[24] Takeshi Yoshimura,et al. Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs , 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..
[25] P. Zarkesh-Ha,et al. A global interconnect design window for a three-dimensional system-on-a-chip , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).
[26] A. Shakouri,et al. Fast thermal simulations of vertically integrated circuits (3D ICs) including thermal vias , 2012, 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.