An Efficient Hardware Implementation of Walsh Hadamard Transform for JPEG XR

Walsh Hadamard Transform (WHT) is an important transformation technique used in image and signal processing applications like image compression, filtering and speech processing. The WHT becomes an automatic choice in JPEG XR image compression standard due to the simple computation technique. The kernel matrix used in WHT consists of only two values namely +1 and -1, hence input coefficients are either added or subtracted. This paper proposes a high throughput pipelined architecture for computing WHT by reusing common sub-expressions. In the proposed design, computation is performed by adding and subtracting the input data and store the intermediate results (sub-expressions) in the register stacks for reuse. The architecture is designed and implemented in XC3S700AN-4 device and maximum frequency of operation obtained is 162 MHz. The comparison of the computing speed of the proposed architecture with the previously available designs has been done based on the throughput which is defined as the time interval for computing overall results of an 8×8 image matrix. The proposed architecture consumes 395 nS time (Throughput) to generate the result of an 8×8 image matrix which is 51% lesser than that of the best available design.

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