Combined Input-Crosspoint Bufiered Packet Switch with Shared Crosspoint Bufiers 1

The amount of memory in bufiered crossbars in combined input-crosspoint bufiered switches is proportional to the number of crosspoints, or O(N 2 ), where N is the number of ports, and to the crosspoint bufier size, which is deflned by the dis- tance between the line cards and the bufiered cross- bar, to achieve 100% throughput under high-speed data ∞ows. A long distance between these two com- ponents can make a bufiered crossbar costly to imple- ment. In this paper, we propose a combined input- shared-crosspoint bufiered packet switch that uses small crosspoint bufiers to support long round-trip times, which consider the distance between the line card and the bufiered crossbar. The proposed switch reduces the required bufier memory of the bufiered crossbar by 50% or more, and uses no speedup.

[1]  Ioannis Papaefstathiou,et al.  Variable packet size buffered crossbar (CICQ) switches , 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).

[2]  Mark J. Karol,et al.  Queueing in high-performance packet switching , 1988, IEEE J. Sel. Areas Commun..

[3]  K. Yoshigoe.  A parallel-polled virtual output queue with a buffered crossbar , 2001 .

[4]  Mounir Hamdi,et al.  MCBF: a high-performance scheduling algorithm for buffered crossbar switches , 2003, IEEE Communications Letters.

[5]  Cyriel Minkenberg,et al.  A four-terabit single-stage packet switch with large round-trip time support , 2002, Proceedings 10th Symposium on High Performance Interconnects.

[6]  Mounir Hamdi,et al.  Practical scheduling algorithms for high-performance packet switches , 2003, IEEE International Conference on Communications, 2003. ICC '03..

[7]  R. Rojas-Cessa,et al.  CIXB-1: combined input-one-cell-crosspoint buffered switch , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).

[8]  Eiji Oki,et al.  A 10Gb / s ( 1 . 25 Gb / s 8 ) 4 2 0 . 25m CMOS / SIMOX ATM Switch Based on Scalable Distributed Arbitration , 1999 .

[9]  Eiji Oki,et al.  A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration , 1999, IEEE J. Solid State Circuits.

[10]  Masayoshi Nabeshima.  Performance Evaluation of a Combined Input- and Crosspoint-Queued Switch , 2000 .

[11]  Satoshi Nojima,et al.  Integrated Services Packet Network Using Bus Matrix Switch , 1987, IEEE J. Sel. Areas Commun..

[12]  Naoaki Yamanaka,et al.  High-speed ATM switch with input and cross-point buffers , 1993 .

[13]  Nick McKeown,et al.  The iSLIP scheduling algorithm for input-queued switches , 1999, TNET.

[14]  R. R. Cessa.  CIXOB-1 : Combined Input-crosspoint-output buffered packet switch , 2001 .

[15]  Eiji Oki,et al.  Round-robin selection with adaptable-size frame in a combined input-crosspoint buffered switch , 2003, IEEE Communications Letters.

[16]  Ken Christensen,et al.  A parallel-polled virtual output queued switch with a buffered crossbar , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).

[17]  Cyriel Minkenberg,et al.  Reducing memory size in buffered crossbars with large internal flow control latency , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[18]  Eiji Oki,et al.  CIXOB-k: combined input-crosspoint-output buffered packet switch , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).