Scaling out Ising machines using a multi-chip architecture for simulated bifurcation

Ising machines are hardware devices that can solve ground-state search problems of Ising spin models and could be of use in solving various practical combinatorial optimization problems. However, large-scale systems have to be implemented by partitioning into subsystems that are hard to synchronize and where communication between them is difficult. Here, we report a scale-out architecture for Ising machines that provides enlarged machine sizes and enhanced processing speeds by using multiple connected chips. The architecture is based on the partitioned version of a quantum-inspired algorithm called simulated bifurcation. To maintain time consistency between multiple chips and a sufficiently small stall rate for every time-evolution step in simulated bifurcation, the architecture relies on an autonomous synchronization mechanism that is implemented in the information exchange processes between neighbouring chips and leads to scalability of computational throughput. Our eight-FPGA (field-programmable gate array) simulated bifurcation machine can obtain high-quality solutions to a 16,384-node MAX-CUT problem in 1.2 ms, which is 828 times faster than an optimized implementation of simulated annealing. Multiple field-programmable gate arrays can be networked to create clustered, scalable architectures that can be used to run partitioned simulated bifurcation algorithms for solving non-deterministic polynomial-time (NP)-hard problems.