New materials for post-Si computing: Ge and GeSn devices

As Si-transistor technology advances beyond the 10 nm node, the device research community is increasingly looking into the possibility of replacing Si with novel, high mobility materials as the transistor channel. Among several possible candidate materials, germanium and germanium-tin alloys (GeSn) have emerged as strong contenders for the next generation of complementary metal oxide semiconductor (CMOS) transistors. This article presents a comprehensive overview of the state of the art in Ge and GeSn transistor research. We address several key material challenges involved in fabricating high-performance Ge/GeSn-based CMOS transistors, such as gate stack formation and achieving low-resistance contacts to transistor source/drain regions. Using Ge/GeSn as channel materials, we present a FinFET-based, Si-compatible CMOS solution for device dimensions expected in the 7 nm technology node, discuss the practical challenges involved in realizing this design, and highlight directions for future research.

[1]  Krishna C. Saraswat,et al.  7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and Sn , 2014, IEEE Transactions on Electron Devices.

[2]  M. Takenaka,et al.  Impact of Plasma Postoxidation Temperature on the Electrical Properties of ${\rm Al}_{2}{\rm O}_{3}/{\rm GeO}_{x}/{\rm Ge}$ pMOSFETs and nMOSFETs , 2014, IEEE Transactions on Electron Devices.

[3]  J. Locquet,et al.  Tensile-Strained GeSn Metal–Oxide–Semiconductor Field-Effect Transistor Devices on Si(111) Using Solid Phase Epitaxy , 2013 .

[4]  M. Takenaka,et al.  Ge gate stacks based on Ge oxide interfacial layers and the impact on MOS device properties , 2013 .

[5]  Y. Yeo,et al.  Ge0.97Sn0.03 p-channel metal-oxide-semiconductor field-effect transistors: Impact of Si surface passivation layer thickness and post metal annealing , 2013 .

[6]  Suyog Gupta,et al.  Hole Mobility Enhancement in Compressively Strained ${\rm Ge}_{0.93}{\rm Sn}_{0.07}$ pMOSFETs , 2013, IEEE Electron Device Letters.

[7]  (110)-oriented germanium-tin (Ge0.97Sn0.03) P-channel MOSFETs , 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

[8]  K. Saraswat,et al.  Material characterization of high Sn-content, compressively-strained GeSn epitaxial films after rapid thermal processing , 2013 .

[9]  R. Lieten,et al.  Tensile strained GeSn on Si by solid phase epitaxy for high mobility FET devices , 2013 .

[10]  Rui Zhang,et al.  High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation , 2013, IEEE Transactions on Electron Devices.

[11]  Y. Yeo,et al.  Germanium–Tin (GeSn) p-Channel MOSFETs Fabricated on (100) and (111) Surface Orientations With Sub-400 $^{\circ}\hbox{C}\ \hbox{Si}_{2}\hbox{H}_{6}$ Passivation , 2013, IEEE Electron Device Letters.

[12]  P. P. Manik,et al.  Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer , 2012 .

[13]  K. J. Kuhn,et al.  Considerations for Ultimate CMOS Scaling , 2012, IEEE Transactions on Electron Devices.

[14]  A. Asenov,et al.  Hole Mobility in Germanium as a Function of Substrate and Channel Orientation, Strain, Doping, and Temperature , 2012, IEEE Transactions on Electron Devices.

[15]  N. Taoka,et al.  High-Mobility Ge pMOSFET With 1-nm EOT $\hbox{Al}_{2} \hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stack Fabricated by Plasma Post Oxidation , 2012, IEEE Transactions on Electron Devices.

[16]  J. Alamo.  Nanometre-scale electronics with III–V compound semiconductors , 2011, Nature.

[17]  Wilfried Vandervorst,et al.  Undoped and in-situ B doped GeSn epitaxial growth on Ge by atmospheric pressure-chemical vapor deposition , 2011 .

[18]  Mitsuru Takenaka,et al.  Suppression of ALD-Induced Degradation of Ge MOS Interface Properties by Low Power Plasma Nitridation of GeO2 , 2011 .

[19]  J. Hartmann,et al.  Low temperature boron and phosphorous doped SiGe for recessed and raised sources and drains , 2011 .

[20]  Mitsuru Takenaka,et al.  Al2O3/GeOx/Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation , 2011 .

[21]  K. Nagashio,et al.  High-Electron-Mobility $\hbox{Ge/GeO}_{2}$ n-MOSFETs With Two-Step Oxidation , 2011, IEEE Transactions on Electron Devices.

[22]  K. Saraswat,et al.  Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial layer to reduce Schottky barrier height , 2011 .

[23]  N. Taoka,et al.  Physical origins of mobility enhancement of Ge p-channel metal-insulator-semiconductor field effect transistors with Si passivation layers , 2010 .

[24]  M Takenaka,et al.  High-Performance $\hbox{GeO}_{2}/\hbox{Ge}$ nMOSFETs With Source/Drain Junctions Formed by Gas-Phase Doping , 2010, IEEE Electron Device Letters.

[25]  K. Saraswat,et al.  Specific Contact Resistivity of Tunnel Barrier Contacts Used for Fermi Level Depinning , 2010, IEEE Electron Device Letters.

[26]  Mitsuru Takenaka,et al.  Surface orientation dependence of interface properties of GeO2/Ge metal-oxide-semiconductor structures fabricated by thermal oxidation , 2009 .

[27]  Heiji Watanabe,et al.  Origin of flatband voltage shift and unusual minority carrier generation in thermally grown GeO2/Ge metal-oxide-semiconductor devices , 2009 .

[28]  Mitsuru Takenaka,et al.  Evidence of low interface trap density in GeO2∕Ge metal-oxide-semiconductor structures fabricated by thermal oxidation , 2008 .

[29]  A. Toriumi,et al.  A Significant Shift of Schottky Barrier Heights at Strongly Pinned Metal/Germanium Interface by Inserting an Ultra-Thin Insulating Film , 2008 .

[30]  Tomonori Nishimura,et al.  Direct Evidence of GeO Volatilization from GeO2/Ge and Impact of Its Suppression on GeO2/Ge Metal–Insulator–Semiconductor Characteristics , 2008 .

[31]  Shinichi Takagi,et al.  Effects of Si passivation on Ge metal-insulator-semiconductor interface properties and inversion-layer hole mobility , 2008 .

[32]  M. Kuijk,et al.  Ohmic contact formation on n-type Ge , 2008 .

[33]  Heiji Watanabe,et al.  Characteristics of Pure Ge3N4 Dielectric Layers Formed by High-Density Plasma Nitridation , 2008 .

[34]  Shinichi Takagi,et al.  Gate dielectric formation and MIS interface characterization on Ge , 2007 .

[35]  Marc Heyns,et al.  Effective electrical passivation of Ge(100) for high-k gate dielectric layers using germanium oxide , 2007 .

[36]  Daniel J. Connelly,et al.  Fermi-level depinning for low-barrier Schottky source/drain transistors , 2006 .

[37]  Satoshi Hashimoto,et al.  Electrical Characterization of Germanium Oxide/Germanium Interface Prepared by Electron-Cyclotron-Resonance Plasma Irradiation , 2005 .

[38]  Marc Heyns,et al.  Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates , 2005 .

[39]  Albert Chin,et al.  Alternative surface passivation on germanium for metal-oxide-semiconductor applications with high-k gate dielectric , 2004 .

[40]  S. Takagi,et al.  Ge metal-insulator-semiconductor structures with Ge3N4 dielectrics by direct nitridation of Ge substrates , 2004 .

[41]  Krishna C. Saraswat,et al.  Local epitaxial growth of ZrO2 on Ge (100) substrates by atomic layer epitaxy , 2003 .

[42]  Stefan Zollner,et al.  Ge–Sn semiconductors for band-gap and lattice engineering , 2002 .

[43]  M. S. Carroll,et al.  Low‐Temperature Preparation of Oxygen‐ and Carbon‐Free Silicon and Silicon‐Germanium Surfaces for Silicon and Silicon‐Germanium Epitaxial Growth by Rapid Thermal Chemical Vapor Deposition , 2000 .

[44]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[45]  Low temperature epitaxy of Si and Si1−xGex by utrahigh vacuum-chemical molecular epitaxy , 1997 .

[46]  S. Jang,et al.  Chemical Vapor Deposition of Epitaxial Silicon‐Germanium from Silane and Germane II . In Situ Boron, Arsenic, and Phosphorus Doping , 1995 .