Reusable IP Analog Circuit Design

As ‘Time to market’ plays a crucial role for successful System on Chip (SoC) business, all chip companies try to drastically reduce development cycle times. Especially in analog circuit design this is an extraordinarily challenging target. Decreasing supply voltages along with the fast introduction of new sub micron technologies and increased performance and functionality would rather suggest an increase of design efforts. But making use of IP-reuse can help a lot to achieve development cycle time reduction. A review of possible reuse methods and comments on their feasibility are presented in this paper

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