A non-iterative effective capacitance model for CMOS gate delay computing

In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Ceff equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Ceff calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.

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