Modeling of Simultaneous Switching Noise in On-Chip and Package Power Distribution Networks Using ConformalMapping, Finite Difference Time Domain and Cavity Resonator Methods

[1]  Andreas C. Cangellaris,et al.  Modeling and simulation of coupled transmission line interconnects over a noisy reference plane , 1993 .

[2]  Andreas C. Cangellaris,et al.  Reference plane parasitics modeling and their contribution to the power and ground path , 1994 .

[3]  Yehea Ismail,et al.  Gasping the impact of on-chip inductance , 2001 .

[4]  Jose E. Schutt-Aine,et al.  Latency insertion method (LIM) for the fast transient simulation of large networks , 2001 .

[5]  H. H. Wu,et al.  Accurate power supply and ground plane pair models , 1998, IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.98TH8370).

[6]  Rajendran Panda,et al.  Design and analysis of power distribution networks in PowerPC microprocessors , 1998, DAC.

[7]  S. R. Vemuru.  Effects of simultaneous switching noise on the tapered buffer design , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Brian Young.  Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages , 2000 .

[9]  Sani R. Nassif,et al.  Fast power grid simulation , 2000, Proceedings 37th Design Automation Conference.

[10]  Tai-Yu Chou,et al.  Capacitance calculation of IC packages using the finite element method and planes of symmetry , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Madhavan Swaminathan,et al.  Analysis of multi-layered irregular power distribution planes with vias using transmission matrix method , 2001, IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565).

[12]  Jinseong Choi.  Modeling of power supply noise in large chips using the finite difference time domain method , 2002 .

[13]  S. Ramo,et al.  Fields and Waves in Communication Electronics , 1966 .

[14]  Robert W. Dutton,et al.  A CAD-oriented modeling approach of frequency-dependent behavior of substrate noise coupling for mixed-signal IC design , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[15]  C.P. Wong,et al.  Electrical design of wafer level package on board for gigabit data transmission , 2003, Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003).

[16]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[17]  Joong-Ho Kim,et al.  Modeling of package and board power distribution networks using transmission matrix and macro-modeling methods , 2002 .

[18]  A. Scarlatti,et al.  An equivalent transmission-line model containing dispersion for high-speed digital lines-with an FDTD implementation , 2001 .

[19]  Marc Belleville,et al.  Inductance and capacitance analytic formulas for VLSI interconnects , 1996 .

[20]  D. Blaauw,et al.  Impact of low-impedance substrate on power supply integrity , 2003, IEEE Design & Test of Computers.

[21]  S. A. Chickamenahalli,et al.  Enhancing power distribution system through 3D integrated models, optimized designs, and switching VRM model , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[22]  Sung-Hwan Min,et al.  Automated Construction of Macromodels from Frequency Data for Simulation of Distributed Interconnect Networks , 2004 .

[23]  Sani R. Nassif,et al.  Multigrid-like technique for power grid analysis , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[24]  Madhavan Swaminathan,et al.  Modeling of multilayered power distribution planes using transmission matrix method , 2002 .

[25]  Wenjian Yu,et al.  Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM , 2003 .

[26]  W. S. Song,et al.  Power distribution techniques for VLSI circuits , 1986 .

[27]  Nanju Na,et al.  Modeling and transient simulation of planes in electronic packages , 2000 .

[28]  Andreas Weisshaar,et al.  Accurate closed-form expressions for the frequency-dependent line parameters of coupled on-chip interconnects on silicon substrate , 2001, IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565).

[29]  H. A. Wheeler.  Transmission-Line Properties of a Strip Line Between Parallel Planes , 1978 .

[30]  M. Swaminathan,et al.  Modeling and simulation of core switching noise on a package and board , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[31]  Allen Taflove,et al.  Computational Electrodynamics the Finite-Difference Time-Domain Method , 1995 .

[32]  C. Nguyen.  Analysis Methods for RF, Microwave, and Millimeter-Wave Planar Transmission Line Structures , 2000 .

[33]  M. Nakhla,et al.  A fast algorithm and practical considerations for passive macromodeling of measured/simulated data , 2002, Electrical Performance of Electronic Packaging,.

[34]  Nanju Na.  Modeling and simulation of planes in electronic packages , 2001 .

[35]  Linda P. B. Katehi,et al.  Application of system-level EM modeling to high-speed digital IC packages and PCBs , 1997 .

[36]  Jifeng Mao,et al.  Effect of substrate resistivity on switching noise in on-chip power distribution networks , 2003, Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).

[37]  L. Smith.  Simultaneous switch noise and power plane bounce for CMOS technology , 1999, IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412).

[38]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[39]  Madhavan Swaminathan,et al.  Modeling of field penetration through planes in multilayered packages , 2001 .

[40]  Sungjun Chun.  Methodologies for modeling simultaneous switching noise in multi-layered packages and boards , 2002 .

[41]  Rajendran Panda,et al.  A methodology for chip-level electromigration risk assessment and product qualification , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[42]  Madhavan Swaminathan,et al.  Modeling of irregular shaped power distribution planes using transmission matrix method , 2001 .

[43]  George Papadopoulos,et al.  Full-wave PEEC time-domain method for the modeling of on-chipinterconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[44]  Zhang Jin,et al.  Physics based modeling of simultaneous switching noise in high speed systems , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[45]  Weimin Shi,et al.  New efficient method of modeling electronics packages with layered power/ground planes , 2002 .

[46]  Malgorzata Marek-Sadowska,et al.  On-chip power supply network optimization using multigrid-based technique , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[47]  Kwang-Ting Cheng,et al.  Analysis of performance impact caused by power supply noise in deep submicron devices , 1999, DAC '99.

[48]  Madhavan Swaminathan,et al.  Modeling of realistic on-chip power grid using the FDTD method , 2002, 2002 IEEE International Symposium on Electromagnetic Compatibility.

[49]  Barry K. Gilbert,et al.  Wave model solution to the ground/power plane noise problem , 1995 .

[50]  Woopoung Kim,et al.  Electromagnetic modelling of switching noise in on-chip power distribution networks , 2003, 8th International Conference on Electromagnetic Interference and Compatibility.

[51]  P. Zarkesh-Ha,et al.  Optimum on-chip power distribution networks for gigascale integration (GSI) , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[52]  Hannu Tenhunen,et al.  Efficient and accurate modeling of power supply noise on distributed on-chip power networks , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[53]  H. A. Wheeler.  Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane , 1977 .

[54]  K. Oh,et al.  Capacitance computations in a multilayered dielectric medium using closed-form spatial Green's functions , 1993 .

[55]  David Overhauser,et al.  Full-chip verification methods for DSM power distribution systems , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[56]  Mattan Kamon,et al.  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.

[57]  Giovanni Ghione,et al.  Parameters of coplanar waveguides with lower ground plane , 1983 .

[58]  John L. Prince,et al.  Simultaneous Switching Noise of CMOS Devices and Systems , 1993 .

[59]  J. S. Neely,et al.  Interconnect and circuit modeling techniques for full-chip power supply noise analysis , 1998 .

[60]  J. L. Prince,et al.  Simultaneous switching ground noise calculation for packaged CMOS devices , 1991 .

[61]  Nanju Na,et al.  Modeling and transient simulation of planes in electronic packages for GHz systems , 1999, IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412).

[62]  Rajendran Panda,et al.  Hierarchical analysis of power distribution networks , 2000, DAC.

[64]  Jose E. Schutt-Aine,et al.  Optimal transient simulation of transmission lines , 1996 .

[65]  Keunmyung Lee,et al.  Modeling and analysis of multichip module power supply planes , 1995 .

[66]  Frederick Warren Grover,et al.  Inductance Calculations: Working Formulas and Tables , 1981 .

[67]  Eby G. Friedman,et al.  Inductive characteristics of power distribution grids in high speed integrated circuits , 2002, Proceedings International Symposium on Quality Electronic Design.

[68]  A. Orlandi,et al.  Internal impedance of conductors of rectangular cross section , 1999 .

[69]  Vijai K. Tripathi,et al.  Quasi-TEM spectral domain approach for calculating distributed inductance and resistance of microstrip on Si-SiO/sub 2/ substrate , 1998 .

[70]  Hannu Tenhunen,et al.  Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits , 2002 .

[71]  Chong-Min Kyung,et al.  A floorplan-based planning methodology for power and clock distribution in ASICs , 1999, DAC '99.

[72]  Michel S. Nakhla,et al.  Analysis of interconnect networks using complex frequency hopping (CFH) , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[73]  Farid N. Najm,et al.  Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[74]  Madhavan Swaminathan,et al.  Capturing via effects in simultaneous switching noise simulation , 2001, 2001 IEEE EMC International Symposium. Symposium Record. International Symposium on Electromagnetic Compatibility (Cat. No.01CH37161).

[75]  H. A. Wheeler.  Formulas for the Skin Effect , 1942, Proceedings of the IRE.

[76]  Massoud Pedram,et al.  Analysis of jitter due to power-supply noise in phase-locked loops , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[77]  A. Weisshaar,et al.  Closed-form expressions for the series impedance parameters of on-chip interconnects on multilayer silicon substrates , 2004, IEEE Transactions on Advanced Packaging.

[78]  Eby G. Friedman,et al.  Inductance/area/resistance tradeoffs in high performance power distribution grids , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[79]  M. Swaminathan,et al.  Efficient construction of two-port passive macromodels for resonant networks , 2001, IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565).

[80]  John M. Cohn,et al.  Managing power and performance for system-on-chip designs using Voltage Islands , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[81]  Madhavan Swaminathan,et al.  Modeling of irregular shaped power distribution networks using transmission matrix method , 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).

[82]  Madhavan Swaminathan,et al.  Model to hardware correlation for power distribution induced I/O noise in a functioning computer system , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[83]  B. Gustavsen,et al.  Enforcing Passivity for Admittance Matrices Approximated by Rational Functions , 2001, IEEE Power Engineering Review.

[84]  P. Silvester,et al.  Modal network theory of skin effect in flat conductors , 1966 .

[85]  Erdem Matoglu,et al.  Statistical design, analysis, and diagnosis of digital systems and embedded RF circuits , 2003 .

[86]  K. Yee.  Numerical solution of initial boundary value problems involving maxwell's equations in isotropic media , 1966 .

[87]  Jiayuan Fang,et al.  A locally conformed finite-difference time-domain algorithm of modeling arbitrary shape planar metal strips , 1993 .

[88]  Jong-Gwan Yook,et al.  System level EM modeling of digital IC packages and PC boards , 1996 .

[89]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[90]  A. Semlyen,et al.  Simulation of transmission line transients using vector fitting and modal decomposition , 1998 .

[91]  大越 孝敬.  Planar circuits for microwaves and lightwaves , 1985 .

[92]  Madhavan Swaminathan,et al.  Modeling of multi-layered power distribution planes including via effects using transmission matrix method , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[93]  R. Simons.  Coplanar waveguide circuits, components, and systems , 2001 .

[94]  Roland Schinzinger,et al.  Conformal Mapping: Methods and Applications , 1991 .

[95]  A. Weisshaar,et al.  CAD-oriented equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate , 2000 .

[96]  W. R. Eisenstadt,et al.  S-parameter-based IC interconnect transmission line characterization , 1992 .

[97]  A. E. Ruehii.  Inductance Calculations in a Complex Integrated Circuit Environment , 2002 .

[98]  Madhavan Swaminathan,et al.  Computation and effect of field penetration through planes in multi-layered package power distribution networks for giga-processors , 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).

[99]  David D. Ling,et al.  Power Supply Noise Analysis Methodology For Deep-submicron Vlsi Chip Design , 1997, Proceedings of the 34th Design Automation Conference.

[100]  Hai Lan,et al.  Accurate closed-form expressions for the frequency-dependent line parameters of on-chip interconnects on lossy silicon substrate , 2001, 2001 IEEE MTT-S International Microwave Sympsoium Digest (Cat. No.01CH37157).

[101]  Analysis of the power plane resonance using the alternating-direction implicit (ADI) FDTD method , 2002, IEEE Antennas and Propagation Society International Symposium (IEEE Cat. No.02CH37313).

[102]  G.A. Katopis,et al.  Delta-I noise specification for a high-performance computing machine , 1985, Proceedings of the IEEE.

[103]  Rob A. Rutenbar,et al.  Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs , 1996 .