IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays

Resistive Crossbar Arrays present an elegant implementation solution for Deep Neural Networks acceleration. The Matrix-Vector Multiplication, which is the corner-stone of DNNs, is carried out in <inline-formula> <tex-math notation="LaTeX">$O(1)$ </tex-math></inline-formula> compared to <inline-formula> <tex-math notation="LaTeX">$O(N^{2})$ </tex-math></inline-formula> steps for digital realizations of <inline-formula> <tex-math notation="LaTeX">$O(log_{2}(N))$ </tex-math></inline-formula> steps for in-memory associative processors. However, the IR drop problem, caused by the inevitable interconnect wire resistance in RCAs remains a daunting challenge. In this article, we propose a fast and efficient training and validation framework to incorporate the wire resistance in Quantized DNNs, without the need for computationally extensive SPICE simulations during the training process. A fabricated four-bit Au/Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/TiN device is modelled and used within the framework with two-mapping schemes to realize the quantized weights. Efficient system-level IR-drop estimation methods are used to accelerate training. SPICE validation results show the effectiveness of the proposed method to capture the IR drop problem achieving the baseline accuracy with a 2% and 4% drop in the worst-case scenario for MNIST dataset on multilayer perceptron network and CIFAR 10 dataset on modified VGG and AlexNet networks, respectively. Other nonidealities, such as stuck-at fault defects, variability, and aging, are studied. Finally, the design considerations of the neuronal and the driver circuits are discussed.

[1]  Bin Gao,et al.  Fully hardware-implemented memristor convolutional neural network , 2020, Nature.

[2]  Chih-Cheng Chang,et al.  Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[3]  E. Neftci,et al.  Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective , 2019, Memristive Devices for Brain-Inspired Computing.

[4]  Peng Lin,et al.  Reinforcement learning with analogue memristor arrays , 2019, Nature Electronics.

[5]  Mohammed E. Fouda,et al.  Mask Technique for Fast and Efficient Training of Binary Resistive Crossbar Arrays , 2019, IEEE Transactions on Nanotechnology.

[6]  Yiran Chen,et al.  Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[7]  Ran El-Yaniv,et al.  Binarized Neural Networks , 2016, ArXiv.

[8]  Jiaming Zhang,et al.  Analogue signal and image processing with large memristor crossbars , 2017, Nature Electronics.

[9]  Kaushik Roy,et al.  Neural network accelerator design with resistive crossbars: Opportunities and challenges , 2019, IBM J. Res. Dev..

[10]  Shimeng Yu,et al.  Neuro-Inspired Computing With Emerging Nonvolatile Memorys , 2018, Proceedings of the IEEE.

[11]  Frederick T. Chen,et al.  RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme , 2015, IEEE Transactions on Computers.

[12]  Mohammed E. Fouda,et al.  Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network Hardware , 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

[13]  Shuying Cheng,et al.  Thermal stability and data retention of resistive random access memory with HfO x /ZnO double layers* , 2017 .

[14]  S. Ambrogio,et al.  Understanding switching variability and random telegraph noise in resistive RAM , 2013, 2013 IEEE International Electron Devices Meeting.

[15]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[16]  Ahmed M. Eltawil,et al.  Minimal Disturbed Bits in Writing Resistive Crossbar Memories , 2018, 2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

[17]  Jinfeng Kang,et al.  Insight into Effects of Oxygen Reservoir Layer and Operation Schemes on Data Retention of HfO2-Based RRAM , 2019, IEEE Transactions on Electron Devices.

[18]  Miao Hu,et al.  ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[19]  Vivienne Sze,et al.  Efficient Processing of Deep Neural Networks: A Tutorial and Survey , 2017, Proceedings of the IEEE.

[20]  Ahmed M. Eltawil,et al.  Modeling and Analysis of Passive Switching Crossbar Arrays , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Zhigang Zeng,et al.  Memristive Quantized Neural Networks: A Novel Approach to Accelerate Deep Learning On-Chip. , 2019, IEEE transactions on cybernetics.

[22]  Farnood Merrikh-Bayat,et al.  Training and operation of an integrated neuromorphic network based on metal-oxide memristors , 2014, Nature.

[23]  Zhengya Zhang,et al.  A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations , 2019, Nature Electronics.

[24]  J. Yang,et al.  Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension , 2018, Nature Nanotechnology.

[25]  Indranil Chakraborty,et al.  Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars , 2017, IEEE Transactions on Emerging Topics in Computational Intelligence.

[26]  John Paul Strachan,et al.  Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors , 2019, Advanced Electronic Materials.

[27]  David Gregg,et al.  Parallel Multi Channel convolution using General Matrix Multiplication , 2017, 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[28]  Catherine E. Graves,et al.  Memristor‐Based Analog Computation and Neural Network Classification with a Dot Product Engine , 2018, Advanced materials.

[29]  Kiyoung Choi,et al.  VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks , 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[30]  Yu Wang,et al.  Stuck-at Fault Tolerance in RRAM Computing Systems , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[31]  Sang Gil Lee,et al.  Four-Bits-Per-Cell Operation in an HfO2 -Based Resistive Switching Device. , 2017, Small.

[32]  Ahmed M. Eltawil,et al.  A Hybrid Approximate Computing Approach for Associative In-Memory Processors , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[33]  Shiping Wen,et al.  CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network , 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  Wenqiang Zhang,et al.  Sign backpropagation: An on-chip learning algorithm for analog RRAM neuromorphic computing systems , 2018, Neural Networks.

[35]  Jürgen Schmidhuber,et al.  Deep learning in neural networks: An overview , 2014, Neural Networks.

[36]  J. Yang,et al.  Memristive crossbar arrays for brain-inspired computing , 2019, Nature Materials.

[37]  Mohammed A. Zidan,et al.  Parasitic Effect Analysis in Memristor-Array-Based Neuromorphic Systems , 2018, IEEE Transactions on Nanotechnology.

[38]  Ahmed M. Eltawil,et al.  A Two-Dimensional Associative Processor , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[39]  Jinseok Kim,et al.  Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics , 2017, ACM J. Emerg. Technol. Comput. Syst..

[40]  Sergey Ioffe,et al.  Batch Normalization: Accelerating Deep Network Training by Reducing Internal Covariate Shift , 2015, ICML.

[41]  Ahmed M. Eltawil,et al.  Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning , 2018, 2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

[42]  Zhigang Zeng,et al.  Memristive LSTM Network for Sentiment Analysis , 2019, IEEE Transactions on Systems, Man, and Cybernetics: Systems.

[43]  Jie Lin,et al.  Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[44]  Bo Hong,et al.  Neural signal analysis with memristor arrays towards high-efficiency brain–machine interfaces , 2020, Nature Communications.

[45]  E. Vianello,et al.  On the Origin of Low-Resistance State Retention Failure in HfO2-Based RRAM and Impact of Doping/Alloying , 2015, IEEE Transactions on Electron Devices.

[46]  Qing Wu,et al.  Efficient and self-adaptive in-situ learning in multilayer memristor neural networks , 2018, Nature Communications.

[47]  Ahmed M. Eltawil,et al.  On-Chip Error-Triggered Learning of Multi-Layer Memristive Spiking Neural Networks , 2020, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[48]  Yiran Chen,et al.  Memristor-Based Design of Sparse Compact Convolutional Neural Network , 2020, IEEE Transactions on Network Science and Engineering.

[49]  Geoffrey E. Hinton,et al.  ImageNet classification with deep convolutional neural networks , 2012, Commun. ACM.