CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development
暂无分享,去创建一个
Gu-Yeon Wei | Paul N. Whatmough | Glenn G. Ko | Marco Donato | David Brooks | Gu-Yeon Wei | D. Brooks | P. Whatmough | M. Donato
[1] Gu-Yeon Wei,et al. A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators , 2019, 2019 Symposium on VLSI Circuits.
[2] Gu-Yeon Wei,et al. DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications , 2018, IEEE Journal of Solid-State Circuits.
[3] Gu-Yeon Wei,et al. A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs , 2019, IEEE Journal of Solid-State Circuits.
[4] Luca P. Carloni,et al. Invited: The case for Embedded Scalable Platforms , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[5] Rob A. Rutenbar,et al. A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm , 2020, 2020 IEEE Symposium on VLSI Circuits.
[6] Gu-Yeon Wei,et al. SMAUG , 2019, ACM Trans. Archit. Code Optim..
[7] Christopher Batten,et al. PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[8] Christopher Torng,et al. INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).
[9] Michael Bedford Taylor,et al. Basejump STL: systemverilog needs a standard template library for hardware design , 2018, DAC.
[10] John Wawrzynek,et al. Chisel: Constructing hardware in a Scala embedded language , 2012, DAC Design Automation Conference 2012.