High-resolution online power monitoring for modern microprocessors

The power consumption of computing systems is nowadays a major design constraint that affects performance and reliability. To co-optimize these aspects, fine-grained adaptation techniques at runtime are of growing importance. However, to use these tools efficiently, fine-grained information about the power consumption of various on-chip components at runtime is required. Therefore, here we propose a novel software-implemented high-resolution (spatial and temporal) power monitoring approach that relies on micro-models to estimate the power consumption of all microarchitectural components inside a processor core. Combined with a self-calibration technique that uses an available on-chip power sensor, our power estimation approach can achieve an accuracy of more than 99 % and provides deep insights about the power dissipation inside a processor core during workload execution.

[1]  Kunle Olukotun,et al.  The Future of Microprocessors , 2005, ACM Queue.

[2]  Bernd Mohr,et al.  Modeling CPU Energy Consumption of HPC Applications on the IBM POWER7 , 2014, 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

[3]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[4]  Rajesh Gupta,et al.  Evaluating the effectiveness of model-based power characterization , 2011 .

[5]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[6]  Weisong Shi,et al.  SPAN: A software power analyzer for multicore computer systems , 2011, Sustain. Comput. Informatics Syst..

[7]  Mani B. Srivastava,et al.  Low-cost estimation of sub-system power , 2012, 2012 International Green Computing Conference (IGCC).

[8]  Karthick Rajamani,et al.  IBM Research Report Online Power and Performance Estimation for Dynamic Power Management , 2006 .

[9]  Christine A. Shoemaker,et al.  Flicker: a dynamically adaptive architecture for power limited multicore systems , 2013, ISCA.

[10]  Norbert Wehn,et al.  Reliable on-chip systems in the nano-era: Lessons learnt and future trends , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Sally A. McKee,et al.  Real time power estimation and thread scheduling via performance counters , 2009, CARN.

[12]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Bishop Brock,et al.  Introducing the Adaptive Energy Management Features of the Power7 Chip , 2011, IEEE Micro.

[14]  Bishop Brock,et al.  Architecting for power management: The IBM® POWER7™ approach , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[15]  Lei He,et al.  Temperature and supply Voltage aware performance and power modeling at microarchitecture level , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Mehdi Baradaran Tahoori,et al.  Aging-Aware Design of Microprocessor Instruction Pipelines , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.