A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique

This paper presents a high linearity dynamic amplifier with an on-chip gain detection technique, which realizes the stabilization of process, voltage, and temperature (PVT) with the real-time fluctuation. Based on the cross-coupled capacitive degeneration topology and characteristics of transistors in weak inversion, according to the simulation results, the proposed dynamic amplifier achieves −80 dB total harmonic distortion (THD) across the wide range of supply voltage and temperature. The prototype amplifier is designed at the supply voltage of 1 V in 28 nm CMOS process, and it dissipates 260 µW at the frequency of 100 MS/s with the maximum output swing of 1.2 Vpp. The power consumption is positively related to the clock frequency.

[1]  Klaas Bult,et al.  A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers , 2018, IEEE Journal of Solid-State Circuits.

[2]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[3]  Kofi A. A. Makinwa,et al.  A Capacitively Degenerated 100-dB Linear 20–150 MS/s Dynamic Amplifier , 2018, IEEE Journal of Solid-State Circuits.

[4]  Yong-Bin Kim,et al.  Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Hae-Seung Lee,et al.  Zero-crossing detector based reconfigurable analog system , 2010, 2010 IEEE Asian Solid-State Circuits Conference.

[6]  Akira Matsuzawa,et al.  A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).